The invention relates to delay lock loops (DLLs). More particularly, the invention relates to a DLL delay line that includes a clock pulse width restoration circuit.
Clock signals are used in virtually every digital integrated circuit (IC) and electronic system to control timing. For example, whenever there is a rising edge on a clock signal, all the flip-flops in a circuit might change state. Clearly, the higher the frequency of the clock signal, the faster the circuit operates. Therefore, much attention has been given to achieving the highest possible clock speeds that can be supported by the clock circuitry.
One problem that typically develops when high-frequency clocks are used is the problem of xe2x80x9cclock skewxe2x80x9d. Clock skew occurs when a clock signal is routed to two or more destinations and, because of varying delays on the clock paths, arrives at the targeted destinations at different times. For example, clock skew can occur when a clock signal is provided to the output pads and also to the internal circuitry of an IC. There might be, for example, a shorter delay in routing the clock signal to the output pads than there is in routing the clock signal to the internal circuitry. In this example, if the internal circuitry is driving the output pads, the clock skew can cause data errors.
A delay lock loop (DLL) is often used to remove clock skew. A DLL corrects the difference in timing between two skewed clock signals by adding a delay to the slower path. The added delay is the additional delay required to give the slower path exactly N clock periods more delay than the faster path, where N is a whole number. Thus, the two active edges arriving at the two target destinations are aligned, with N clock periods of delay between the two clock signals. A DLL typically continuously monitors the relative delay between a feedback clock signal and an input clock signal, adding an additional unit delay to the output clock signal when the feedback clock is too fast and subtracting a unit delay when the feedback clock is too slow.
DLLs typically contain several delay lines. A delay line is a number of delay elements coupled in series. The delay elements in a delay line are generally designed to have delays as nearly identical as possible. Output signals from the delay line are typically tapped after each delay element or each group of delay elements. The number of unit delays added to the input clock signal is determined by which tap signal is selected to provide the DLL output signal.
FIG. 1 shows a known DLL. The DLL of FIG. 1 includes a phase shifter circuit (clock phase shifter) 101 and two delay circuits A and B (102 and 103, respectively), all coupled in series. Each of these elements includes at least one delay line. In the pictured DLL, delay circuit A includes a 256-tap delay line, and delay circuit B includes four 128-tap delay lines 104a-104d. Delay circuit A is typically used to control feedback delays, while delay circuit B is used to generate quarter phasing of the input clock CLKIN (hence the four delay lines in delay circuit B).
Delay circuit B can include any number of delay lines having any number of taps. The more delay lines that are included in delay circuit B, the higher the number of clock phases that can be provided by the DLL. For example, when four delay lines are included, quarter phasing is supported by the DLL. When six delay lines are included, one-sixth phasing is supported, and so forth. Additionally, the greater the number of taps included in each delay line, the lower the input clock frequency that can be handled by delay circuit B.
Delay circuits B provides five output signals to an output generator circuit 105. Signal P00 is a delayed version of clock signal CLKIN_PS, provided by phase shifter circuit 101. Signals P25, P50, P75, and P100 are each shifted an additional quarter phase from clock signal P00. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Output generator circuit 105, selects one of the delay line output signals as the output clock signal CLKOUT for the DLL. The output clock signal CLKOUT drives a clock network 106, e.g., for the integrated circuit including the DLL. From clock network 106 a feedback clock signal CLKFB feeds back to phase shifter circuit 101.
Phase shifter circuit 101 can optionally be used to add skew (delay offset) between signals CLKIN and CLKFB by phase shifting signals CLKIN and CLKFB to provide phase shifted signals CLKIN_PS and CLKFB_PS. Phase detector 108 compares the phase of the phase shifted feedback clock signal CLKFB_PS with the phase of the phase shifted input clock signal CLKIN_PS, and reports to the control logic (107) which of the two signals is ahead of the other. In response, the control logic instructs delay circuit A to either increase or decrease the amount of delay added to the clock path. Delay circuit A is xe2x80x9clockedxe2x80x9d when it has achieved phase alignment between signals CLKIN_PS and CLKFB_PS.
Phase Detector 109 compares the phase of signals P00 and P100, and reports to the control logic which signal is ahead of the other. In response, the control logic instruct delay circuit B to either increase or decrease the amount of delay added to the clock path, thereby bringing signals P00 and P100 closer and closer to being in phase. Delay circuit B is xe2x80x9clockedxe2x80x9d when it has achieved phase alignment between P00 and P100. Typically, this locking occurs when the delay through delay circuit B has become equal to the clock period of signal CLKIN. Control logic block 107 accepts input signals from blocks 101, 102, 103, 104a-d, 108, and 109, and provides output signals to blocks 101, 102, 103, 104a-d, 105, 108, and 109.
Each delay line typically includes a series of delay elements providing the tap signals and a multiplexer circuit that selects one of the tap signals as the delay line output signal. FIG. 2 illustrates an exemplary 128-tap delay line. For example, four delay lines similar to that shown in FIG. 2 can be used to implement delay circuit B of FIG. 1. However, typically all delay lines in the DLL use the same basic circuitry, to match performance and facilitate the tuning of the clock signal. The number of delay elements in each delay line can vary widely. Typically, the number of delay elements is selected to be a power of two, i.e., 2{circumflex over ( )}N, where N is an integer. This practice simplifies the multiplexer control logic.
Delay line 104 includes a series of 128 tap delays. Tap delay circuit 201 provides 128 tapped output signals D[0-127]. FIG. 3 shows one implementation of tap delay circuit 201, which includes 128 unit delay elements TAP0-TAP127 coupled in series. Each delay element provides one tap output signal. FIG. 4 shows one implementation of a single unit delay element TAPX, which includes four inverters 402a-402d coupled in series. The four inverters typically include transistors of the same size and configuration in each delay element, to equalize as much as possible the delay through each delay element. Many other implementations of a delay line delay element are well known and commonly used.
Returning now to FIG. 2, the tap signals are provided to the multiplexer circuit, which in this instance includes four multiplexer stages 202-205 and a multiplexer controller circuit 206. Multiplexer stage 1 is a 4-to-1 multiplexer that accepts 128 input tap signals and selects 32 of the input signals, which are provided to multiplexer stage 2. Multiplexer stage 2 is another 4-to-1 multiplexer that accepts 32 input tap signals and selects 8 of the signals, which are then provided to multiplexer stage 3. Multiplexer stage 3 reduces the number of tap signals to two, and the final multiplexer stage selects the one tap signal that is used as the output signal for the delay line.
The selection of tap signals is performed by multiplexer controller circuit 206. Multiplexer controller circuit 206 is controlled by state machine logic in control logic 107 (see FIG. 1). Thus, multiplexers 202-205 select a tap signal from tap delay circuit 201 based on the values of status signals received from the appropriate phase detector (phase detector 108 for delay circuit A, and phase detector 109 for delay circuit B).
FIG. 5 illustrates a phenomenon that often occurs in delay lines, and can seriously impede DLL performance. Delay lines typically have at least a slight imbalance between their rising and falling propagation delays. For example, each inverter in a delay line includes a P-channel transistor (which controls the rising propagation delay) and an N-channel transistor (which controls the falling propagation delay). Each inverter can be designed to balance these two delays, insofar as is possible. Typically, each delay element is intentionally designed to balance its aggregate rising and falling delays. However, due to external factors such as variations in process, voltage supplied to the transistors, and local temperature, the P-channel devices might be faster or slower than the N-channel devices. This imbalance can occur not only in delay lines, but in the multiplexer circuit as well, for example. However, the imbalance is magnified in the delay lines, due to the large number of serially-connected delay elements in these structures.
Suppose, for example, that a clock pulse includes a rising edge followed a short time later by a falling edge. If the rising propagation delay is consistently longer than the falling propagation delay, the rising edge of the clock pulse will be delayed relative to the falling edge. Thus, each delay element will provide a slightly narrower high clock pulse than the previous delay element in the delay line. If the delay line includes enough delay elements, and if the per element imbalance is large enough, an input clock pulse can completely vanish before the end of the delay line, as shown in FIG. 5. Conversely, in this example, if the rising propagation delay is consistently shorter than the falling propagation delay, the high pulse will gradually increase in width as it traverses the delay line.
FIG. 5 illustrates the effect of this phenomenon on a narrow clock pulse provided to the 256-tap delay line 102 of FIG. 1. If each delay element includes four inverters (as shown in FIG. 4), 256-tap delay line 102 includes up to 1024 inverters coupled in series, depending on which tap is selected. In the illustrated example, the rising propagation delay is consistently longer than the falling propagation delay. Therefore, a narrow high clock pulse (see waveform 501) provided to the input terminal IN of delay line 102 is eliminated entirely by the time the signal reaches the output terminal OUT (see waveform 502).
The effect of this deterioration is to limit the pulse width allowed on clock signals provided to the DLL that includes the delay line. This requirement, in turn, limits the frequency range of the supported input clock signal.
Therefore, it is desirable to provide delay lines for DLL circuits that can reduce or eliminate the effects of clock pulse width deterioration.
The invention provides delay lock loops (DLLs) that include delay line circuits with an optional clock pulse width restoration feature. According to one aspect of the invention, a DLL includes optional inversions before and after at least one of the delay lines included in the DLL. Because two inversions are provided, the overall logic of the delay line is preserved. A DLL typically includes several different delay lines. Therefore, by selectively inverting the clock signal between the delay lines, the effect of each delay line on the clock pulse width can be balanced to provide an output clock signal having a pulse width closer to that of the input clock than would be achievable without the use of such selective inversion. In embodiments where the DLL forms a portion of a programmable logic device (PLD), the optional inversions can be controlled, for example, by configuration memory cells of the PLD. Other aspects of the invention include various programmable delay circuits that can be used in DLLs as described above.
According to one embodiment, the invention provides a DLL that includes an input clock terminal, a feedback clock terminal, an output clock terminal, a phase shifter circuit, first and second phase detectors, first and second programmable inversion circuits, first and second delay circuits, an output generator circuit, and a control circuit.
The phase shifter circuit has a first input terminal coupled to the input clock terminal of the DLL, a second input terminal coupled to the feedback clock terminal of the DLL, and first and second output terminals. The first phase detector is coupled to the first and second output terminals of the phase shifter circuit. The first programmable inversion circuit has an input terminal coupled to the first output terminal of the phase shifter circuit, an output terminal, and a control terminal. The first delay circuit has an input terminal coupled to the output terminal of the first programmable inversion circuit, and an output terminal. The second programmable inversion circuit has an input terminal coupled to the output terminal of the first delay circuit, an output terminal, and a control terminal.
The second delay circuit has an input terminal coupled to the output terminal of the second programmable inversion circuit, and a plurality of output terminals. The second phase detector has first and second input terminals coupled to first and last ones of the output terminals of the second delay circuit. The output generator circuit has a plurality of input terminals coupled to the output terminals of the second delay circuit, and an output terminal coupled to the output clock terminal of the DLL. Finally, the control circuit is coupled to each of the phase shifter circuit, the first and second phase detectors, the first and second delay circuits, and the output generator circuit.
In some embodiments, the control terminal of the first programmable inversion circuit is coupled to the control terminal of the second programmable inversion circuit. Thus, both inversions are enabled or disabled together, preserving unchanged the logical functionality of the DLL. In some embodiments, the DLL forms a portion of a programmable logic device (PLD), and the control terminals of the programmable inversion circuits are coupled to one or more configuration memory cells of the PLD.
In some embodiments, the DLL forms a portion of an integrated circuit (IC) that also includes a clock network coupled between the output clock terminal and the input clock terminal of the DLL.
In some embodiments, the second delay circuit also includes third, fourth, and fifth programmable inversion circuits coupled to each clock input and output terminal. These additional programmable inversion circuits are controlled in a fashion similar to the first and second programmable inversion circuits.
In some embodiments, the phase shifter circuit also includes third, fourth, fifth, and sixth programmable inversion circuits coupled to each of the clock input and output terminals of a clock phase shifter. The third, fourth, fifth, and sixth programmable inversion circuits are controlled in a fashion similar to the first and second programmable inversion circuits.
According to another embodiment, a DLL includes an input clock terminal; a feedback clock terminal; an output clock terminal; a phase shifter circuit; first and second phase detectors; first and second delay circuits; first, second, and third programmable inversion circuits; an output generator circuit; and a control circuit.
The phase shifter circuit has a first input terminal coupled to the input clock terminal of the DLL, a second input terminal coupled to the feedback clock terminal of the DLL, and first and second output terminals. The first phase detector is coupled to the first and second output terminals of the phase shifter circuit. The first delay circuit has an input terminal coupled to the first output terminal of the phase shifter circuit, and an output terminal. The first programmable inversion circuit has an input terminal coupled to the output terminal of the first delay circuit, an output terminal, and a control terminal. The second programmable inversion circuit has an input terminal coupled to the output terminal of the first programmable inversion circuit, an output terminal, and a control terminal.
The second delay circuit has an input terminal coupled to the output terminal of the first programmable inversion circuit, and an output terminal. The third programmable inversion circuit has an input terminal coupled to the output terminal of the second delay circuit, an output terminal, and a control terminal.
The second phase detector has a first input terminal coupled to the output terminal of the second programmable inversion circuit and a second input terminal coupled to the output terminal of the third programmable inversion circuit. The output generator circuit has a first input terminal coupled to the output terminal of the second programmable inversion, a second input terminal coupled to the output terminal of the third programmable inversion circuit, and an output terminal coupled to the output clock terminal of the DLL. Finally, the control circuit is coupled to each of the phase shifter circuit, the first and second phase detectors, the first and second delay circuits, and the output generator circuit.
According to yet another embodiment, a DLL includes an input clock terminal; a feedback clock terminal; an output clock terminal, first, second, third, and fourth programmable inversion circuits; a phase shifter circuit; first and second phase detectors, first and second delay circuits; an output generator circuit, and a control circuit.
The first programmable inversion circuit has an input terminal coupled to the input clock terminal of the DLL, an output terminal, and a control terminal. The second programmable inversion circuit has an input terminal coupled to the feedback clock terminal of the DLL, an output terminal, and a control terminal. The phase shifter circuit has a first input terminal coupled to the output terminal of the first programmable inversion circuit, a second input terminal coupled to the output terminal of the second programmable inversion circuit, and first and second output terminals. The third programmable inversion circuit has an input terminal coupled to the first output terminal of the phase shifter circuit, an output terminal, and a control terminal. The fourth programmable inversion circuit has an input terminal coupled to the second output terminal of the phase shifter circuit, an output terminal, and a control terminal. The first phase detector is coupled to the output terminals of the first and second programmable inversion circuits.
The first delay circuit has an input terminal coupled to the output terminal of the third programmable inversion circuit, and an output terminal. The second delay circuit has an input terminal coupled to the output terminal of the first delay circuit, and a plurality of output terminals. The second phase detector has a first input terminal coupled to a first one of the output terminals of the second delay circuit and a second input terminal coupled to the last one of the output terminals of the second delay circuit. The output generator circuit has a plurality of input terminals coupled to the output terminals of the second delay circuit, and an output terminal coupled to the output clock terminal of the DLL. Finally, the control circuit is coupled to each of the phase shifter circuit, the first and second phase detectors, the first and second delay circuits, and the output generator circuit.
According to another aspect of the invention, a programmable delay circuit includes an input terminal, an output terminal, first and second programmable inversion circuits, and a delay line. The first programmable inversion circuit has an input terminal coupled to the input terminal of the delay circuit, an output terminal, and a control terminal. The delay line has an input terminal coupled to the output terminal of the first programmable inversion circuit, and an output terminal. Finally, the second programmable inversion circuit has an input terminal coupled to the output terminal of the delay line, an output terminal, and a control terminal.
In some embodiments, the control terminal of the first programmable inversion circuit is coupled to the control terminal of the second programmable inversion circuit. In some embodiments, the delay circuit forms a portion of a PLD, and the control terminal of the first programmable inversion circuit is coupled to a first configuration memory cell of the PLD. In other embodiments, the control terminal of the first programmable inversion circuit is coupled to a first configuration memory cell of the PLD, and the control terminal of the second programmable inversion circuit is coupled to a second configuration memory cell of the PLD.
According to another embodiment, a programmable delay circuit includes an input terminal; first and second output terminals; first, second, and third programmable inversion circuits; and a first delay line. The first programmable inversion circuit has an input terminal coupled to the input terminal of the programmable delay circuit, an output terminal, and a control terminal. The second programmable inversion circuit has an input terminal coupled to the output terminal of the first programmable inversion circuit, an output terminal coupled to the first output terminal of the programmable delay circuit, and a control terminal. The first delay line has an input terminal coupled to the output terminal of the first programmable inversion circuit, and an output terminal. Finally, the third programmable inversion circuit has an input terminal coupled to the output terminal of the first delay line, an output terminal coupled to the second output terminal of the programmable delay circuit, and a control terminal.
According to another embodiment, a programmable delay circuit includes an input terminal; an output terminal; first, second, third, and fourth programmable inversion circuits; and first and second delay lines. The first programmable inversion circuit has an input terminal coupled to the input terminal of the programmable delay circuit, an output terminal, and a control terminal. The first delay line has an input terminal coupled to the output terminal of the first programmable inversion circuit, and an output terminal. The second programmable inversion circuit has an input terminal coupled to the output terminal of the first delay line, an output terminal, and a control terminal. The third programmable inversion circuit has an input terminal coupled to the output terminal of the second programmable inversion circuit, an output terminal, and a control terminal. The second delay line has an input terminal coupled to the output terminal of the second programmable inversion circuit, and an output terminal. Finally, the fourth programmable inversion circuit has an input terminal coupled to the output terminal of the second delay line, and an output terminal coupled to the output terminal of the programmable delay circuit.